Currently, a Thin Film Field Effect Transistor display panel includes: an effective display region AA containing a plurality of pixel electrodes, a Vertical Shift Register (VSR) configured to turn on and turn off a Thin Film Transistor (TFT) connected with each of the pixel electrodes in the display region AA, and an integrated circuit (IC) chip configured to provide signals to the VSR. FIG. 1 is a schematic view showing the structure of the TFT display panel in the prior art.
FIG. 2 is a schematic view showing the structure of a gate driving circuit with the VSR in the prior art. As shown in FIG. 2, the VSR includes a plurality of cascaded Shift Register (SR) units, a signal line providing a start pulse signal STV, a signal line providing a reset signal GRESET, a signal line providing a first clock signal (CLK1) and a signal line providing a second clock signal (CLK2). Each of the stages of the VSR circuit includes one SR unit, and pulses of the first clock signal CLK1 and pulses of the second clock signal CLK2 are alternatively provided to implement the function of the SR unit by an enable circuit, where the first pulse of the first clock signal CLK1 occurs within the time duration of a pulse of the start pulse signal STV. FIG. 3 is a timing diagram showing the operation of SR units of the left VSR, where a phase of the first clock signal CLK1 is inverse to that of the second clock signal CLK2. The operation process of the gate driving circuit is as follows: when STV=1, a high level pulse is outputted to an input end of the shift register unit SR1 connected with a first row of the pixel units, so that the first stage of shift register unit SR1 is turned on to output a high gate level to the TFT display panel, but the other stages of shift register units are turned off, meanwhile, an input end of the next stage of shift register unit SR3 is applied by a high level pulse to turn on the shift register unit SR3. When the shift register unit SR3 outputs a high level signal, the other stages of the shift register units are turned off, meanwhile, an input end of the next stage of shift register unit SR5 is applied by a high level pulse, and so on, until the last stage of shift register unit is applied by a high level pulse. Output signals of the various shift register units SR1 to SR2N−1 are represented by OUT1 to OUT2N−1, as shown in FIG. 3.
In the technical solution described above, each of the shift register units controls only one gate line. Since the shift register units occupy more than 40% of the area of the VSR, it is difficult to achieve a narrow frame design because of the large number of VSR TFTs required.